A method for compressing a data structure representing a layout of a Vary Large Scale Integration device, block, or set of layout cells (i.e.- device) and especially a method for reducing the size of a representation of non functional elements within said VLSI device.
Prior art methods of manufacturing, multi-layered VLSI layout require to insert non functional elements between functional elements, whenever said functional elements are relatively far from each other. Functional elements are usually parts of layout cells or wires used to connect layout cells. The insertion of non functional element assures that each layer of said multi layered layout is planar.
Usually, said layouts are generated by layout editors. Said editors usually have a design rule check tool. Said layout editors are usually able to compress a representation of functional elements, but are not adapted to compress a representation of non functional elements. Accordingly. The representation of non functional elements are vary large and reduced the efficiency of layout processing.
There is a need of an improved method that overcomes the disadvantages of prior art methods for manufacturing multi layered layouts and compress the representation of multi layered layout of VLSI devices.